VLSI Architectures for Neural Network Based Image Compression

This book attempts to develop a Low Power VLSI Architectures for Neural Network based Image Compression. The power is a very important criterion, since the neural network is a parallel massive structure and hence consumes more power. Hence in this book it is explained to develop, design and implement dedicated low power VLSI architectures for image compression based on neural networks, optimizing for speed, area and power. In this book it is also explained new architecture for Neural Network based image compression for ASIC implementation. The results for different architectures are also explained with the ASIC implementation results obtained for complexity, power, area and speed.