Performance Analysis of SoC Architectures based on Network Calculi

This thesis describes a method for static performance analysis for obtaining upper bounds on delay and buffering requirements in a SoC architecture. The method is based on network calculus theory known as LR servers. This network calculus is extended and applied to make it support SoC performance analysis. Performance requirements of subsystems are elegantly captured as traffic flows and associated latency constraints. The SoC infrastructure is modeled as a set of LR servers to validate that the worst-case delays in handling the traffic flows meet the latency constraints. The power of the performance analysis method is demonstrated by analyzing several schedule and interconnect variants for a multi-channel DVB-T set-top box case study. The influence of the frequency of the memory system and the pipeline degree of the traffic streams is shown. Furthermore, the influence of the packet size on the buffering requirements is analyzed. Key architecture choices, such as schedule or interconnect variant, can be varied easily to support exploration of architecture options.