On The Design of Low Power CMOS (SA-ADCs) for Biomedical Applications

This book presents three different CMOS realizations of an 8-bit successive approximation analog-to-digital converter (SA-ADC) for biomedical applications. The architecture of the proposed SA-ADCs consist of a sample and hold, a comparator, a successive approximation register (SAR) controller, and an 8-bit digital-to-analog converter. Each building block of the SA-ADC has been reviewed with different architectures in a unique chapter including the simulation results for each architecture for different frequency applications. The proposed SA-ADCs are presented, compared and simulated using 90nm CMOS technology file on LT-spice-IV. In each realization, the SAR controller is implemented using D-flip flop or hybrid latch-flip flop. The best proposed SA-ADC realization has been obtained from the different proposed realizations. According to the simulation results, the best proposed SA-ADC consumes 200nW from 1V power supply and 88.76 nW from 0.85V supply voltage without additional analog circuits. Layout and post layout have been extracted with a real recorded EEG signal for the best proposed SA-ADC. Static and Dynamic performance matrices were obtained for the proposed SA-ADCs.