MODELLING AND DESIGN OF MODIFIED SDM BASED NETWORK ON CHIP

Moore¿s law has driven the scaling of digital electronic devicesdimensions and performances over the last 50 years. As a result, logic components in a System-On-Chip (SoC) have shown dramatic performance improvement. On the other hand, an on-chip interconnects which was considered only as a parasitic load before 1990s became the real performance bottleneck due to its extremely reduced cross section dimension. The ever decreasing interconnects cross section dimensions give rise to increase in resistance. Putting all these together, degradation of the RC time constant of on-chip metal wires becomes more serious. As a result, the continuous performance degradation of on-chip Cu/low k interconnects is one of the greatest challenges to keep Moore's law alive while the scaling of transistors dimension has provided relentless delay improvement.