Memory Customization in multiple processors Systems on chip

With the change in time, there is increase in the demand of embedded system applications with advanced technologies. Multiprocessor Systems-on-Chip (MPSoC¿s) become usual in embedded systems to provide required power efficient systems. The power consumed and performance of the system majorly depends on the memory organization of the system and hence requiring system with low power memory organizations. The first issue is multiple processor synchronization. The second issue is the use of replacement policies in SPM. The third major problem is the need of a simulator which provides the shared memory environment for multiprocessors. The requirement of an efficient, high performance cache replacement policy is next issue in case of memory systems. The fifth issue is the implementation of an efficient replacement policy in SPM. The next issue in heterogeneous processors on a single chip is to deal with the cache coherence problem which results in inconsistency of data. The seventh issue is to find solution of cache conflict miss problem. The next issue is to find the best topology and routing algorithm in each scenariös.