Improved Architecture Of 256 Bit CSLA For Reduced Area Applications

In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessity of portable systems. In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSlA) is one of the fastest adders used in many data - processing processors. The structure of CSlA is such that there is further scope of reducing the area.Simple and efficient gate ¿ level modification is used to develop an area- efficient carry select adder by sharing the common Boolean logic term (CBL) is proposed. After logic simplification and sharing partial circuit, only one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation are needed. Through the multiplexer, the correct output is selected according to the logic states of the carry in signal.