FPGA Implementation of Priority Rank Based Routing Algorithm

Network on chip has become a promising solution pertaining to developing a large number of cores on the chip to obtain top rated. This built in framework redundancy regarding NoC provides the potential to design the fault-tolerant routing protocol to enhance this trustworthiness. Network on chip is definitely an interconnection concerning many control aspects and routers. There are several alternatives for the occurrence of faults in the network. These kinds of faults degrade the performance of the network. Some fault-tolerant algorithms are proposed to support special cases of faults, such as one-faulty routers, convex or concave regions. These algorithms either disable the healthy components or require a large number of virtual channels to avoid deadlock.