Efficient and Flexible Cryptographic Co-Processor Architecture

In todays networks security is becoming more and more important. Public Key Cryptography, which is a necessary building block for this, places a high workload on the server in client-server networks. A co-processor can be used to shoulder some of this workload. However, as the networks become increasingly heterongenous, the server must also be able to communicate with clients utilizing different cryptographic schemes. Thus, the two main design goals for such a co-processor are efficiency and flexibility. In context of server application, efficiency is measured as high throughput instead of low latency. Flexibility aims for the support of different cryptographic schemes and an easy expandability. This work proposes a generic co-processor architecture for RSA, Elliptic Curve Cryptography, and Pairing-Based Cryptography, which utilizes a combined HW/SW-design allowing high flexibility without sacrificing efficiency. Based on a new classification of parallelization possibilities, it exploits parallelization on all abstraction levels as long as this furthers throughput. The feasibility and usefulness of the architecture is verified by means of a prototype implementation.