Design of Low Power Adder Using Double Gate & MTCMOS Technology

Other than reducing leakage power the MTCMOS technique could be used for a different design goal. In MOS Current Mode Logic (MCML) the operating supply voltages can be reduced by using this MTCMOS technology. We can design a low power standard cell library for the adder circuit using this MTCMOS technology which can be standardized at logic levels; it includes a collection of components. This leads to even reduction in power since MTCMOS technique is used. These cells can be designed by varying the size of the sleep transistor to handle different loads and this can be used for minimum area, high speed applications. A new approach can be made for sizing the sleep transistor which indeed leads to reduction of total width of the sleep transistor for a MTCMOS circuit by making an assumption of a cell used and also by the placement of the sleep transistor. This may result in minimizing the parasitic resistances of the virtual ground net; and also leads to leakage power reduction. By increasing the efficiency of packing currents into the sleep transistor more accurate results can be obtained. Future work should include the designing and fabrication of larger MTCMOS circuits.