De-Noising System for Speech Signal Enhancement In Digital Hearing AID

In this research work, an efficient pipelined architecture for Real-Valued FFT/RIFFT processor and modified Wiener filter is proposed to improve the noise degradation in digital hearing aids for reducing area and power. The FFT is utilized to calculate the DFT in a sequential manner. In hearing aid application the FFT algorithm requires more computations because of the conversions of time-to-frequency and frequency-to-time has to be done in real time. The FFT computation of real signal using conventional techniques requires more hardware space with high power consumption. To reduce the hardware space and power consumption an RFFT/RIFFT processor is designed by using an efficient pipelined architecture. In the proposed architecture of RFFT, three blocks does the processing, they are butterfly unit, shuffling unit, modified canonical signed digit multiplier (CSDM). The modified complex multiplier uses the technique of modified CSDM. The twiddle factor values are pre-computed in the RFFT computation and by operating, shifting and addition; the real multiplier count can be reduced.