ASIC Design for a Coherent Optical Receiver DSPU

The exponential growth of the internet traffic makes it necessary to increase the transmission capacity of the backbone optical transmission system. The coherent optical quadrature PSK (QPSK) with polarization multiplex quadruple channel capacity over the intensity modulation scheme. This upgrades existing 10 Gbit/s links to 40 Gbit/s. This book introduces you to the practicle implementation of the receiver DSPU ASIC of such a system. Chapter 1 introduces the design problem. Chapter 2 starts with an introduction to the optical synchronous QPSK transmission systems and discusses the carrier & data recovery algorithms. Chapter 2 concludes with an introduction to the DSPU ASIC architecture. Chapter 3 discusses the implementation of the DSPU ASIC. The chapter starts with an introduction to the 130 nm technology node and then discuss transmission line implementation issues, DSPU input interface design, and the full DSPU implementation. Finally, test results are presented. Chapter 4 introduces a novel clock skew estimation algorithm. This algorithm calculates the clock skew when process variations and nonuniform temparature varitions are present.