Testing Chips with Mesh-Based Network-on-Chip

Global interconnect solutions based on long wires, like buses, are being replaced by solutions based on shared and segmented wires, like Networks-on-Chip (NoCs), to reduce the cost of global interconnect. A conventional Test Access Mechanism (TAM), which consists of long wires, is also subject to these problems. For this reason, this book studies the reuse of on-chip networks for test data transportation, avoiding dedicated TAMs. This book presents an overall test methodology for NoC-based SoCs which consists of steps to build optimized test wrappers and test scheduling. The test wrappers hide the NoC from the rest of the test architecture, thus, the cores and the test equipment work exactly like they would work in a conventional test architecture. Thus, the proposed wrapper is compatible with previous approaches, like the IEEE Std. 1500. The test scheduling optimizes the chip test length without requiring full knowledge of the NoC, contributing to the generality of the proposed test methodology. Several benchmarks are applied to the conventional and to the proposed test approaches to compare the resulting chip test length and silicon area overhead.