Scalable and low power N.O.C design for reconfigurable system

A scalable and low power network on chip for reconfigurable router is proposed in this book. Verilog Hardware Description Language is used for the design entry of this router. For simulation and synthesis MODELSIM EDITION10.3 and XILINX ISE Design Suite 13.4 are used respectively. Five innovative routers and four links are designed and simulated, synthesized to get the desired results. In the first phase the proposed reconfigurable system routers provides the designing of the various innovative Routers (RRIE, HRRLPHP, EDEEHT, and SRRODFB) along with their performance comparison. In the second phase links are designed (HSLPL, LMSTRDP, LMRTP) using MUX gating and various encoding decoding techniques for reducing power along with their simulation results. Results obtained show less power consumption and less switching transactions as compared to original links.