Low Power Array Multipliers

In recent years, power dissipation is one of the biggest challenges in VLSI design. Multipliers are the main sources of power dissipation in DSP blocks. Power optimization has to be implemented on all components of the processor. In this project, the design and power comparison of the low power unsigned array multipliers and low power Baugh-Wooley multipliers using different types of adder units are analyzed. The fundamental units to design a multiplier are adders. The proposed multiplier is designed by using different types of full adder and half adder units. The design of full adder and half adder for low power is obtained and the low power units are implemented on the proposed multiplier and the results are analyzed for better performance. The designs are done using TANNER SEDIT tool and simulated using TSPICE. The experimental Tanner SPICE results show that the transistor count and the power required are significantly reduced in the proposed design over the existing design.