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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

von Anupam Chattopadhyay und Zheng Wang
Hardcover - 9789811010729
106,99 €
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Weitere Formate

Softcover - 9789811093210
106,99 €

Autorenfreundlich Bücher kaufen?!

Weitere Formate

Softcover - 9789811093210
106,99 €

Beschreibung

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. 

Details

Verlag Springer Singapore
Ersterscheinung 05. Juli 2017
Maße 23.5 cm x 15.5 cm
Gewicht 500 Gramm
Format Hardcover
ISBN-13 9789811010729
Auflage 1st ed. 2018
Seiten 197

Schlagwörter

Computerhardware, Electronic Circuits and Systems, Hardware Performance and Reliability, Schaltkreise und Komponenten (Bauteile)

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