Designing A Flash ADC With a New Structure of 1-N Encoder

In this book a new structure of 1-N coder which is a part of an ADC architecture is implemented and compared with priority encoder which is another alternative(it is explained as well). 2:1 muxes are used in the architecture of 1-N encoder. Also the study includes shematic and layout apperance of other blocks. Cadence IC 5141 package and CMOS TSMC 0.18um library are used in the design. The power consumption is 30uw under the power supply -0.9 to +0.9 and effective area of the chip is 2400 micrometers square. Flash ADC architecture is the most simple one , thats way this type of ADC is presented . Simulation results which are enough to understand how ADCs work are also presented for both alternative. Aditionally ADC parameters (static and dynamic) and other ADC architectures is mentioned with details.Finally It is possible to learn from this book main concepts of microelectronics and how digital and analog CMOS circuits work. Readers can design a flash ADC easily with other alternatives after examine this study. I believe that informations included in this book is fine to begin with ADCs and microelectronics.