CMOS Sample and Hold Circuits

Open-loop sample and hold topologies generally provide the fastest implementation of the sampling function. However, the precision obtained with such configurations is typically much lower than can be achieved with alternative closed-loop architecture. In design where an MOS transistor is used as sampling switch, input-dependent charge associated with the fast turn-off of the switch is often the principal source of sampling error. This charge injection introduces a pedestal error, in the hold mode that results in both nonlinearity and gain error. Since the resistance of switch is nonlinear as the input voltage varies, a nonlinear voltage appears at the output of the switch. To minimize the magnitude of distortion terms, the resistance is linearized and reduced. By appropriately sizing the device, a compromise can be reached between the size of switch resistance and hold capacitance. This book bringsforth the non-linearities associated with a sampling switch along with different design criteria viz. speed, power, resolution, linearity, noise and harmonic analysis.