A Jittered-Sampling Correction Technique of ADCs

In Analogue to Digital Converters (ADCs) jittered sampling raises the noise floor; this leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This research studies a technique that compensate for the effects of jittered. A thorough understanding of sampling in various data converters is complied. A novel design technique based on linear approximation is proposed to counter the effects of clock jitter in ADCs. The system consists of a circuit that performs linear approximation of the incoming signal to an ADC at the time a possibly jittered clock is ticked to estimate the correct value of the sample. Since jitter is essentially caused by phase noise, the jitter is itself estimated using phase demodulation. To avoid introduction of even more noise sources passive and differential approaches have been selected. This approach resulted in improvement in the SNR of 8.09 dB. This corresponds to 1.34 bits of resolution gain in ENOB.