{"product_id":"systemverilog-for-verification-a-guide-to-learning-the-testbench-language-features-von-chris-spear-greg-tumbush","title":"SystemVerilog for Verification","description":"\n                                \n                \u003cp\u003e\n                                        Based on the highly successful second edition, this extended edition of \n                    \n                    \u003ci\u003eSystemVerilog for Verification: A Guide to Learning the Testbench Language Features\u003c\/i\u003e\n                                         teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. It contains materials for both the full-time verification engineer and the student learning this valuable skill.\n                \n                \u003c\/p\u003e\n                                \n                \u003cp\u003eIn the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and then use that context to demonstrate the language features,  including the advantages and disadvantages of different styles, allowing readers to choose between alternatives. This textbook contains end-of-chapter exercises designed to enhance students’ understanding of the material. Other features of this revision include:\u003c\/p\u003e\n                                \n                \u003cul\u003e\n                                        \n                    \u003cli\u003eNew sections on static variables, print specifiers, and DPI from the 2009 IEEE language standard\u003c\/li\u003e\n                                        \n                    \u003cli\u003eDescriptions of UVM features such as factories, the test registry, and the configuration database\u003c\/li\u003e\n                                        \n                    \u003cli\u003eExpanded code samples and explanations \u003c\/li\u003e\n                                        \n                    \u003cli\u003eNumerous samples that have been tested on the major SystemVerilog simulators\u003c\/li\u003e\n                                    \n                \u003c\/ul\u003e\n                                \n                \u003cp\u003e\n                                        \n                    \u003ci\u003eSystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Third Edition \u003c\/i\u003e\n                                        is suitable for use in a one-semester SystemVerilog course on SystemVerilog at the undergraduate or graduate level. Many of the improvements to this new edition were compiled through feedback provided from hundreds of readers.\n                \n                \u003c\/p\u003e\n                                \n                \u003cbr\u003e\n                            \n            \u003cdiv class=\"aw-variant-hidden-subtitle-div\" id=\"aw-variant-subtitle-9781489995001\"\u003e\u003ch3\u003eA Guide to Learning the Testbench Language Features\u003c\/h3\u003e\u003c\/div\u003e\u003cdiv class=\"aw-variant-hidden-subtitle-div\" id=\"aw-variant-subtitle-9781461407140\"\u003e\u003ch3\u003eA Guide to Learning the Testbench Language Features\u003c\/h3\u003e\u003c\/div\u003e","brand":"Libri","offers":[{"title":"Softcover - 9781489995001","offer_id":39417171738717,"sku":"9781489995001","price":69.54,"currency_code":"EUR","in_stock":true},{"title":"Hardcover - 9781461407140","offer_id":39276656951389,"sku":"9781461407140","price":117.69,"currency_code":"EUR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0940\/0622\/files\/f5595e64-7e1e-4e5b-83ea-7e38f0590864.jpg?v=1775796456","url":"https:\/\/shop.autorenwelt.de\/products\/systemverilog-for-verification-a-guide-to-learning-the-testbench-language-features-von-chris-spear-greg-tumbush","provider":"Autorenwelt Shop","version":"1.0","type":"link"}