{"product_id":"low-leakage-sram-memory-von-debasis-mukherjee","title":"Low Leakage SRAM Memory","description":"\u003cp\u003eI present some techniques to decrease the gate and other leakage dissipation in Deep Sub-Micron SRAM memories. This book reviews detail SRAM operations. This book also reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Finally, the book explores different circuit techniques to reduce the leakage power consumption. The W\/L ratios are calculated from the equations of current in transistors (Linear and Saturation mode) for smooth read-write operation of both 0 and 1. I use W1\/W3 = 1.5 and W4\/W6 = 1.5. I first designed conventional SRAM memory and observed leakage current in various technology. In 90 nm technology conventional SRAM shows a leakage current of 1.87nA at steady state. Data retention gated-ground cache (DGR-cache) method reduces the leakage current to 100pA. Drowsy cache method reduces the leakage current to 84pA.\u003c\/p\u003e\u003cdiv class=\"aw-variant-hidden-subtitle-div\" id=\"aw-variant-subtitle-9786205517116\"\u003e\u003ch3\u003eDesign of Low Power High Performance SRAMMemory using Gate Leakage ReductionTechnique\u003c\/h3\u003e\u003c\/div\u003e","brand":"Autorenwelt Shop","offers":[{"title":"Softcover - 9786205517116","offer_id":40810301685853,"sku":"9786205517116","price":43.9,"currency_code":"EUR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0940\/0622\/files\/a1e567d3-f643-4d65-962b-cb22a688169d.png?v=1769668828","url":"https:\/\/shop.autorenwelt.de\/products\/low-leakage-sram-memory-von-debasis-mukherjee","provider":"Autorenwelt Shop","version":"1.0","type":"link"}