{"product_id":"formal-equivalence-checking-and-design-debugging-von-kwang-ting-tim-cheng-shi-yu-huang","title":"Formal Equivalence Checking and Design Debugging","description":"\n                                \n                \u003cem\u003eFormal Equivalence Checking and Design Debugging\u003c\/em\u003e\n                                 covers  two major topics in design verification: logic equivalence checking  and design debugging. The first part of the book reviews the design  problems that require logic equivalence checking and describes the  underlying technologies that are used to solve them. Some novel  approaches to the problems of verifying design revisions after  intensive sequential transformations such as retiming are described in  detail. \n                \n                \u003cbr\u003e\n                                  The second part of the book gives a thorough survey of previous and  recent literature on design error diagnosis and design error  correction. This part also provides an in-depth analysis of the  algorithms used in two logic debugging software programs, ErrorTracer  and AutoFix, developed by the authors. \n                \n                \u003cbr\u003e\n                                  \n                \n                \u003cem\u003eFrom the Foreword:\u003c\/em\u003e\n                                 \n                \n                \u003cbr\u003e\n                                  `With the adoption of the \n                \n                \u003cem\u003estatic sign-off\u003c\/em\u003e\n                                 approach to verifying  circuit implementations the application-specific integrated circuit  (ASIC) industry will experience the first radical methodological  revolution since the adoption of logic synthesis. Equivalence checking  is one of the two critical elements of this methodological revolution.  This book is timely for either the designer seeking to better  understand the mechanics of equivalence checking or for the CAD  researcher who wishes to investigate well-motivated research problems  such as equivalence checking of retimed designs or error diagnosis in  sequential circuits.'\n                \n                \u003cbr\u003e\n                                  Kurt Keutzer, University of California, Berkeley\n            \n            \u003cdiv class=\"aw-variant-hidden-subtitle-div\" id=\"aw-variant-subtitle-9780792381846\"\u003e\u003ch3\u003e\u003c\/h3\u003e\u003c\/div\u003e\u003cdiv class=\"aw-variant-hidden-subtitle-div\" id=\"aw-variant-subtitle-9781461376064\"\u003e\u003ch3\u003e\u003c\/h3\u003e\u003c\/div\u003e","brand":"Libri","offers":[{"title":"Hardcover - 9780792381846","offer_id":50818955974,"sku":"9780792381846","price":192.59,"currency_code":"EUR","in_stock":true},{"title":"Softcover - 9781461376064","offer_id":39415693312093,"sku":"9781461376064","price":192.59,"currency_code":"EUR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0940\/0622\/files\/ef5ea8ca-fdf0-4fe4-b9af-86e9e73972c2.jpg?v=1774758115","url":"https:\/\/shop.autorenwelt.de\/products\/formal-equivalence-checking-and-design-debugging-von-kwang-ting-tim-cheng-shi-yu-huang","provider":"Autorenwelt Shop","version":"1.0","type":"link"}