{"product_id":"direct-transistor-level-layout-for-digital-blocks-von-prakash-gopalakrishnan-rob-a-rutenbar","title":"Direct Transistor-Level Layout for Digital Blocks","description":"\n                                Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing\/power are poorly handled in a fixed cell library. \n                \n                \u003cbr\u003e\n                                \n                \u003cstrong\u003eDirect Transistor-Level Layout For Digital Blocks\u003c\/strong\u003e\n                                 proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. \n                \n                \u003cbr\u003e\n                                The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout.\n                \n                \u003cbr\u003e\n                                \n                \u003cstrong\u003eDirect Transistor-Level Layout For Digital Blocks\u003c\/strong\u003e\n                                 is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.\n            \n            \u003cdiv class=\"aw-variant-hidden-subtitle-div\" id=\"aw-variant-subtitle-9781402076657\"\u003e\u003ch3\u003e\u003c\/h3\u003e\u003c\/div\u003e\u003cdiv class=\"aw-variant-hidden-subtitle-div\" id=\"aw-variant-subtitle-9781475779516\"\u003e\u003ch3\u003e\u003c\/h3\u003e\u003c\/div\u003e","brand":"Libri","offers":[{"title":"Hardcover - 9781402076657","offer_id":51335056198,"sku":"9781402076657","price":106.99,"currency_code":"EUR","in_stock":true},{"title":"Softcover - 9781475779516","offer_id":39416691523677,"sku":"9781475779516","price":106.99,"currency_code":"EUR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0940\/0622\/files\/4c2d9aaa-07c0-4fec-9356-32cd1de28f18.jpg?v=1770527085","url":"https:\/\/shop.autorenwelt.de\/products\/direct-transistor-level-layout-for-digital-blocks-von-prakash-gopalakrishnan-rob-a-rutenbar","provider":"Autorenwelt Shop","version":"1.0","type":"link"}