{"product_id":"design-and-implementation-of-a-multicore-processor-using-fpga-von-ali-j-ibada","title":"Design and Implementation of a Multicore Processor Using FPGA","description":"\u003cp\u003eThis book presents a study of multicore RISC processor by using FPGA. A 32-bit single cycle MIPS processor is designed using VHDL, which can execute 50 instructions. To reach parallel processing by exploiting Instruction Level Parallelism (ILP), two-way superscalar MIPS processor is designed by duplicating some components of single cycle MIPS processor and added hazard unit. Then, the single cycle MIPS processor subdivided to five pipeline stages 5-stages to obtain pipelined MIPS processor. To increase processor performance memory hierarchy is exploited by adding cache memory to pipeline MIPS processor. A Multicore MIPS processor is achieved by connecting two of complete single core together; these cores operate as separate independent processors within a single chip. Coherency problems are solved by using MESI protocol. All processors are designed using Xilinx ISE 13.4 Design Suite. The entire processor design is configured on a Xilinx Spartan-3AN FPGA starter kit, and the results have been displayed on the 2×16 LCD internal screen of the kit and external VGA screen.\u003c\/p\u003e\u003cdiv class=\"aw-variant-hidden-subtitle-div\" id=\"aw-variant-subtitle-9783330073845\"\u003e\u003ch3\u003e\u003c\/h3\u003e\u003c\/div\u003e","brand":"Libri","offers":[{"title":"Softcover - 9783330073845","offer_id":39420603236445,"sku":"9783330073845","price":69.9,"currency_code":"EUR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0940\/0622\/files\/49c4842b-2ee4-4984-95e6-b439f9b95e33.jpg?v=1773119695","url":"https:\/\/shop.autorenwelt.de\/products\/design-and-implementation-of-a-multicore-processor-using-fpga-von-ali-j-ibada","provider":"Autorenwelt Shop","version":"1.0","type":"link"}