{"product_id":"asic-design-and-synthesis-rtl-design-using-verilog-von-vaibbhav-taraate","title":"ASIC Design and Synthesis","description":"This  book describes simple to complex ASIC design practical scenarios using  Verilog. It builds a story from the basic fundamentals of ASIC designs  to advanced RTL design concepts using Verilog. Looking at current trends of  miniaturization, the contents provide practical information on the  issues in ASIC design and synthesis using Synopsys DC and their  solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs,  low-power design techniques, DFT, pre-layout STA and the overall ASIC  design flow with case studies. The contents of this book will be useful  to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.\u003cbr\u003e\n                \u003cp\u003e\u003c\/p\u003e\n            \u003cdiv class=\"aw-variant-hidden-subtitle-div\" id=\"aw-variant-subtitle-9789813346413\"\u003e\u003ch3\u003eRTL Design Using Verilog\u003c\/h3\u003e\u003c\/div\u003e\u003cdiv class=\"aw-variant-hidden-subtitle-div\" id=\"aw-variant-subtitle-9789813346444\"\u003e\u003ch3\u003eRTL Design Using Verilog\u003c\/h3\u003e\u003c\/div\u003e","brand":"Libri","offers":[{"title":"Hardcover - 9789813346413","offer_id":32973910376541,"sku":"9789813346413","price":213.99,"currency_code":"EUR","in_stock":true},{"title":"Softcover - 9789813346444","offer_id":39742822318173,"sku":"9789813346444","price":149.79,"currency_code":"EUR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0940\/0622\/files\/56e1d397-9ae4-434d-9e6b-54389f6cd13a.jpg?v=1746422333","url":"https:\/\/shop.autorenwelt.de\/products\/asic-design-and-synthesis-rtl-design-using-verilog-von-vaibbhav-taraate","provider":"Autorenwelt Shop","version":"1.0","type":"link"}