{"product_id":"hybrid-models-for-power-estimation-in-cmos-vlsi-von-kuntavait-redddy","title":"Hybrid Models for Power Estimation in CMOS VLSI","description":"\u003cp\u003eTran et al. (2005) proposed a power estimation model for digital\u003c\/p\u003e\u003cp\u003eCMOS circuits. The circuit was divided into five sections and the power\u003c\/p\u003e\u003cp\u003edissipation of each part has been estimated individually. Further the\u003c\/p\u003e\u003cp\u003eimplemented gates were also counted, the proposed power investigation\u003c\/p\u003e\u003cp\u003emodel suggest early guidelines for design of circuits. The leakage power\u003c\/p\u003e\u003cp\u003eestimation is most important factor the study of design feasibility.\u003c\/p\u003e\u003cp\u003eDerakhshandeh et al. (2005) identified the relationship between the leakage\u003c\/p\u003e\u003cp\u003epower and threshold voltage, where initially the number of input gates were\u003c\/p\u003e\u003cp\u003eidentified, followed by identifying the number of inputs to the gates and their\u003c\/p\u003e\u003cp\u003ecorresponding states. The predicted results on benchmark ICs reported\u003c\/p\u003e\u003cp\u003eimproved accuracy than the conventional methods of estimation.\u003c\/p\u003e\u003cp\u003eLigang et al. (2006) introduced neural network models for power\u003c\/p\u003e\u003cp\u003eestimation for VLSI circuits. In the proposed study the authors used ISCAS89\u003c\/p\u003e\u003cp\u003ebenchmark circuits and the corresponding experimental results were noted.\u003c\/p\u003e\u003cp\u003eThe neural network based power estimation techniques produced better\u003c\/p\u003e\u003cp\u003eresults as compared to the conventional methods such as Monte-Carlo and\u003c\/p\u003e\u003cp\u003eother statistical techniques. A linear programming based leakage power\u003c\/p\u003e\u003cp\u003eestimation technique has been proposed by Chen et al. (2006), where Genetic\u003c\/p\u003e\u003cp\u003eAlgorithm was implemented for Minimum Leakage Vector (MLV) searching,\u003c\/p\u003e\u003cp\u003ethe leakage power is estimated on gate level by linear programming method.\u003c\/p\u003e\u003cp\u003eThe study assists in reducing the leakage power of VLSI circuits with easy\u003c\/p\u003e\u003cp\u003eimplementations.\u003c\/p\u003e\u003cp\u003eChaudhry et al. (2006) presented accurate power estimation\u003c\/p\u003e\u003cp\u003estrategy by extracting the switching and clock activity of macro power\u003c\/p\u003e\u003cp\u003emodels. Do et al. (2007) discussed a high power estimation models for\u003c\/p\u003e\u003cp\u003eproposed 2-kB 6T - SRAM array, in the proposed study the authors computed\u003c\/p\u003e\u003cp\u003ethe threshold leakage by combining the probing methodology. The memory\u003c\/p\u003e\u003cdiv class=\"aw-variant-hidden-subtitle-div\" id=\"aw-variant-subtitle-9787694546922\"\u003e\u003ch3\u003e\u003c\/h3\u003e\u003c\/div\u003e","brand":"Autorenwelt Shop","offers":[{"title":"Softcover - 9787694546922","offer_id":46741094433093,"sku":"9787694546922","price":33.0,"currency_code":"EUR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0940\/0622\/products\/875d6571-1680-4d63-a89e-8c80c0d8b1f5.jpg?v=1695206462","url":"https:\/\/shop.autorenwelt.de\/en\/products\/hybrid-models-for-power-estimation-in-cmos-vlsi-von-kuntavait-redddy","provider":"Autorenwelt Shop","version":"1.0","type":"link"}