{"product_id":"designing-reliable-and-efficient-networks-on-chips-von-srinivasan-murali","title":"Designing Reliable and Efficient Networks on Chips","description":"\n                                \n                \u003cp\u003e\n                                        Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of \n                    \n                    \u003cem\u003eDesigning Reliable and Efficient Networks on Chips \u003c\/em\u003e\n                                        is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.\n                \n                \u003c\/p\u003e\n                            \n            \u003cdiv class=\"aw-variant-hidden-subtitle-div\" id=\"aw-variant-subtitle-9789048182008\"\u003e\u003ch3\u003e\u003c\/h3\u003e\u003c\/div\u003e","brand":"Libri","offers":[{"title":"Softcover - 9789048182008","offer_id":39416675565661,"sku":"9789048182008","price":160.49,"currency_code":"EUR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0940\/0622\/files\/d09721f6-69d3-4654-8cac-4ef55a0c71c2.jpg?v=1772089416","url":"https:\/\/shop.autorenwelt.de\/en\/products\/designing-reliable-and-efficient-networks-on-chips-von-srinivasan-murali","provider":"Autorenwelt Shop","version":"1.0","type":"link"}