{"product_id":"a-pipelined-multi-core-machine-with-operating-system-support-hardware-implementation-and-correctness-proof-von-petro-lutsyk-jonas-oberhauser-wolfgang-j-paul","title":"A Pipelined Multi-Core Machine with Operating System Support","description":"\n                                \n                \u003cp\u003eThis work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.\u003c\/p\u003e\n                                \n                \n                \u003cp\u003e\n                                        It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:\n                    \n                    \u003cbr\u003e\n                                    \n                \u003c\/p\u003e\n                                \n                \n                \u003cp\u003e\n                                        • MIPS instruction set architecture (ISA) for application and for system programming\n                    \n                    \u003cbr\u003e\n                                    \n                \u003c\/p\u003e\n                                \n                \n                \u003cp\u003e• cache coherent memory system\u003c\/p\u003e\n                                \n                \n                \u003cp\u003e• store buffers in front of the data caches\u003c\/p\u003e\n                                \n                \n                \u003cp\u003e• interrupts and exceptions\u003c\/p\u003e\n                                • memory management units (MMUs)\n                \n                \u003cp\u003e\u003c\/p\u003e\n                                \n                \n                \u003cp\u003e• pipelined processors: the classical five-stage pipeline is extended by two pipeline\u003c\/p\u003e\n                                \n                \n                \u003cp\u003estages for address translation\u003c\/p\u003e\n                                \n                \n                \u003cp\u003e• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)\u003c\/p\u003e\n                                \n                \n                \u003cp\u003e• I\/O-interrupt controller and a disk\u003c\/p\u003e\n                                \n                \n                \u003cp\u003e \u003c\/p\u003e\n                            \n            \u003cdiv class=\"aw-variant-hidden-subtitle-div\" id=\"aw-variant-subtitle-9783030432423\"\u003e\u003ch3\u003eHardware Implementation and Correctness Proof\u003c\/h3\u003e\u003c\/div\u003e","brand":"Libri","offers":[{"title":"Softcover - 9783030432423","offer_id":39423922503773,"sku":"9783030432423","price":53.49,"currency_code":"EUR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0940\/0622\/files\/d6bde223-ce6f-41d0-947c-9f8d7a18ae0a.jpg?v=1773551504","url":"https:\/\/shop.autorenwelt.de\/en\/products\/a-pipelined-multi-core-machine-with-operating-system-support-hardware-implementation-and-correctness-proof-von-petro-lutsyk-jonas-oberhauser-wolfgang-j-paul","provider":"Autorenwelt Shop","version":"1.0","type":"link"}